CPUID Intel&AMD

[Razor]

I looked in here but http://download.intel.com/design/pro...als/253668.pdf found absolutly nothing.

Basicly i need realistic cpu speed calculation.

[Muetze1]

Boy, do not be so stupid!

Zitat:

Zitat von Razor

I looked in here but http://download.intel.com/design/pro...als/253668.pdf found absolutly nothing.

What's the title of the document from that link?

Zitat:

Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3A: System Programming Guide (Part 1)

And what did I wrote?

Zitat:

Zitat von Muetze1

Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3B: System Programming Guide (Part 2)

[Razor]

Sh#! thanks Muetze ill look in to it and ofcourse after i finish it post a working prototype.

[lbccaleb]

extract the package from:

dsp-worx.de

and look at the file "CPUMeter.pas"! i think this can help you ;-)

edit:
also have a look at "FastcodeCPUID.pas"!

[Razor]

It has to be the TIME-STAMP COUNTER otherwise i am stupid as a rock.

Zitat:

TIME-STAMP COUNTER
The Intel 64 and IA-32 architectures (beginning with the Pentium processor) define a
time-stamp counter mechanism that can be used to monitor and identify the relative
time occurrence of processor events. The counter’s architecture includes the
following components:
• TSC flag — A feature bit that indicates the availability of the time-stamp counter.
The counter is available in an if the function CPUID.1:EDX.TSC[bit 4] = 1.
• IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in P6 family and
Pentium processors) — The MSR used as the counter.
• RDTSC instruction — An instruction used to read the time-stamp counter.
• TSD flag — A control register flag is used to enable or disable the time-stamp
counter (enabled if CR4.TSD[bit 2] = 1).
The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,
Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors) is a 64-bit
counter that is set to 0 following a RESET of the processor. Following a RESET, the
counter increments even when the processor is halted by the HLT instruction or the
external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause
the time-stamp counter to stop.
Processor families increment the time-stamp counter differently:
• For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4
processors, Intel Xeon processors (family [0FH], models [00H, 01H, or 02H]);
and for P6 family processors: the time-stamp counter increments with every
internal processor clock cycle.

Zitat:

IA32_TIME_STAMP_COUNTER = $10; MSR REGISTER

The internal processor clock cycle is determined by the current core-clock to busclock
ratio. Intel® SpeedStep® technology transitions may also impact the
processor clock.• For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and
higher]); for Intel Core Solo and Intel Core Duo processors (family [06H], model
[0EH]); for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors
(family [06H], model [0FH]): the time-stamp counter increments at a constant

edit2/ lbccaleb,If it shows speed from cpu its usefull.

[Razor]

lbccaleb,its usefull but no cpu speed :pale:

[Razor]

Here i made something...Its interesting goo look. :wink:

[Razor]

Well?Nobody? :shock:

[DevidEspenschied]

Zitat:

Zitat von Razor

A friend said i have to readmsr the address 0x19.

Simply have a look at Volume 2 of this document: here

Appendix B (page 469) contains the model-specific registers, which are described for the corresponding processor technology.

[Razor]

I did that read everything however i need to extract the VID-Voltage Id.
IA32_PERF_STATUS is the msr address.

Delphi-Quellcode:

function tform1.getcoremulti:integer;
 var

 eax,edx:dword;
 begin
  RdMSR($198, eax,edx) ;
  result:=     eax SHR 8 and $ff
 end;

However how to read voltage?